ldx — RTL simulation acceleration

Measured results. Every number on this page is a wall-clock measurement of a real run on the named hardware, with functional output checked against a reference simulator.

The approach in one paragraph

ldx accelerates RTL simulation two ways. First, compile the design: the DUT is synthesized (yosys) into a single-cycle native state machine instead of being interpreted event-by-event — available standalone or hot-swapped into a running nvc simulation (--accel). Second, make the simulation resident on an FPGA processor array: a mesh of RISC-V cores with nearest-neighbor mailbox routing runs compiled design partitions in parallel, with the host CPU (or, in progress, the array itself) running the testbench.

The 10-million-transfer FIFO benchmark

Yuri Panchul's challenge testcase: a_plus_b_using_wrapped_fifos (three wrapped FIFOs with valid/ready feedback), 10 M transfers, functionally correct, target < 10 s on the ZCU104 board. All rows below are measured; correctness is a transfer-count + data-checksum match against the iverilog/vvp golden (checksum 1280000000).

The on-board number is 1.36 s — 7.4× under the 10 s target (7.35 M transfers/s on one A53 core), ~77× faster than the M4 vvp baseline and ~266× faster than vvp on the x86 desktop.

Processor array on silicon — ZCU104, 8×8 = 64 RISC-V cores @ 200 MHz

The mailbox array (VexRiscv cores, URAM private memory, hardware XY wormhole routing, BRAM link FIFOs) is built, placed, and measured on the ZCU104 — timing closed at 200 MHz, 61% LUT. Measured on the board:

What this is good for — and honestly, what it isn't: the array wins on throughput (many independent simulations at once — regression farms, parameter sweeps) and on large partitioned designs. A single small design does not parallelize: our own benchmark of a 5×5 array against Verilator on one small DUT measured 0.41× — slower than Verilator on a laptop. Per-core speed came from real engineering, each step measured: compiler flags, 1-cycle fetch, and a barrel shifter took the xorshift kernel from 235 to 18 cycles/eval (13×). Known cost: URAM private memory adds ~2× latency on data-heavy workloads versus the cycle-accurate simulation model — FPGA numbers are the ones quoted.

Where this beats a CPU as designs scale — and where it honestly doesn't — is charted with measured anchor points and labeled model lines on the scaling outlook page, including how much of a full IC fits at each array size.

nvc --accel — compiled DUT inside a live simulation

The same compiled-state-machine engine, hot-swapped into a running nvc simulation so the testbench stays fully standard. Measured, output-checked:

The pattern is the finding: speedup tracks per-cycle combinational weight. Compute-heavy designs gain 7–9×; a light FIFO design gains 1–2× because testbench scheduling, which --accel deliberately leaves untouched, dominates.

Portability — the same array RTL across vendors

Methodology

• Wall-clock times, measured on the named hardware; no projections, no multiplied factor chains.
• Every accelerated run is checked against a reference (vvp golden checksum, FIPS SHA-256 vectors, or lock-step Verilator).
• Build and run scripts live in the repository; numbers cite the machine they were taken on.